Title :
Timing optimization of mixed static and domino logic
Author :
Zhao, Min ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
31 May-3 Jun 1998
Abstract :
A timing optimization algorithm dealing with circuits containing mixed domino and static logic is described. Transistor-level node timing constraints of domino logic is described. The optimization procedure preserves the requirements of maintaining adequate noise margins by constraining the sizing procedure. After sizing, charge-sharing problems are identified with a new method and rectified
Keywords :
circuit CAD; circuit optimisation; integrated circuit noise; integrated logic circuits; logic CAD; timing; charge-sharing problems; mixed static/domino logic; noise margins; sizing procedure constraint; timing optimization algorithm; transistor-level node timing constraints; Circuit analysis; Circuit noise; Clocks; Constraint optimization; Contacts; Flip-flops; Logic circuits; Logic design; Sequential circuits; Timing;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705262
