Title :
Researches of Test Nodes Selection of Analog Circuit
Author :
Xu Qing-yao ; Cui Shao-hui ; Han Lu-jie ; Deng Shi-jie
Author_Institution :
Ordnance Eng. Coll., Shijiazhuang, China
Abstract :
Test nodes selection of analog circuit has great significance on fast, accurate circuit diagnosis, reduce test cost. For the lack of the current test nodes selection method of analog circuit, a test nodes selection method of analog circuit based on chaos immune clone selection optimization algorithm is presented in this paper. This method improves the efficiency and accuracy of test node selection. Finally the validity of this method is presented through circuit simulation.
Keywords :
analogue circuits; circuit optimisation; circuit testing; analog circuit; chaos immune clone selection optimization algorithm; circuit diagnosis; circuit simulation; test cost reduction; test node selection method; Analog circuits; Chaos; Circuit faults; Cloning; Genetic algorithms; Heuristic algorithms; Optimization; analog circuit; chaos immune clone selection algorithm; test nodes optimal selection;
Conference_Titel :
Computer Science and Electronics Engineering (ICCSEE), 2012 International Conference on
Conference_Location :
Hangzhou
Print_ISBN :
978-1-4673-0689-8
DOI :
10.1109/ICCSEE.2012.367
