Highly reliable interconnect technology featuring 90 nm DRAM integration

Author

Chung, U-in ; Choi, Siyoung ; Choi, Gil-Heyun

Author_Institution

Process Dev. Team, Samsung Electron. Co. Ltd, Kyunggi, South Korea

fYear

2002

fDate

2002

Firstpage

247

Lastpage

249

Abstract

Reliable interconnection with low resistance is substantially required on DRAM with 90 nm design rule in terms of its integration and functionality. Several key interconnect technologies, including poly metal gate, W bitline, contact and via processes using advanced CVD-Al, are described. Full metal interconnected DRAM exhibits excellent performance and even further scalability.

Keywords

DRAM chips; electric resistance; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; 90 nm; Al; CVD-Al contact processes; CVD-Al via processes; DRAM design rule; DRAM functionality; DRAM integration; W; W bitline; interconnect technologies; interconnection resistance; metal interconnected DRAM; poly metal gate; reliable interconnect technology; scalability; Capacitors; Contact resistance; Etching; Filling; Home appliances; Random access memory; Research and development; Scalability; Substrates; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014947

Filename

1014947

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1901187