A novel CMP application on the fabrication of dual-damascene structures for advanced copper/low-k interconnections

Author

Hu, Shao-Chung ; Chen, Hsueh-Chung ; Fang, Liang-Yuan ; Wang, Chien-Mei ; Hung, Cheng-Yu ; Hsieh, Wen-Yi ; Yen, Po-Wen

Author_Institution

Central Res. & Dev. Div., United Microelectron. Corp., Hsin-Chu, Taiwan

fYear

2002

fDate

2002

Firstpage

253

Lastpage

255

Abstract

In this paper, a novel integration process on the fabrication of dual-damascene (DD) structures in the via first scheme to achieve high performance and reliable BEOL interconnections for advanced copper/low-k application is reported. In addition to the conventional gap-fill polymer (GFP) etch back process, this unique process utilized chemical-mechanical polishing (CMP) on the planarization of GFP. The implementation of GFP-CMP and comparisons with conventional etch back processes were presented. A robust GFP-CMP process in terms of defectivity and hard mask loss was developed. Flat and residual free surfaces after GFP-CMP were found. As a result, recess and fence free DD structures were observed after trench patterning. Comparable shorts yield, via resistance, and wire resistance were obtained. Decent yield on a 2 M SRAM test vehicle was demonstrated. Finally, comparable cost to the GFP-EB is possible to be achieved. This novel process is capable of extending the DD copper integration into the sub-0.18 μm technology node.

Keywords

DRAM chips; chemical mechanical polishing; copper; dielectric thin films; electric resistance; encapsulation; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; permittivity; 0.18 micron; 2 Mbit; CMP; Cu; DD copper integration; GFP planarization; GFP-CMP; SRAM test vehicle; chemical-mechanical polishing; copper/low-k interconnections; defectivity; dual-damascene structures; fence free DD structure; flat residual-free surface; gap-fill polymer etch back process; hard mask loss; integration process; recess free DD structure; reliable BEOL interconnections; shorts yield; technology node; trench patterning; via resistance; wire resistance; Chemical processes; Copper; Etching; Fabrication; Planarization; Polymers; Random access memory; Robustness; Surface resistance; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014949

Filename

1014949