Title :
A simple statically reconfigurable processor architecture
Author :
Moosa, Azmath ; Aneesh, Mohammed
Author_Institution :
Dept. of Electron. Eng., Pondicherry Univ., Pondicherry, India
Abstract :
A reconfigurable Processor architecture is presented that has been designed prioritizing modularity, scalability and simplicity. Modular design enables swapping of functional units within the main processing core while maintaining the same programming model. This ensures that the associated software tools chain such as Assembler and Compiler need not be redesigned. Scalable design enables reconfiguring the datapath width to suite application requirements without redesigning the processor architecture or making changes to the software program already written. Applications for such design range from academia where real world performance of many proposed Adder/Multiplier structures may be tested; to data centers where the nature of operation to be performed on massive chunks of data changes regularly requiring ASIC like performance.
Keywords :
VLSI; adders; application specific integrated circuits; field programmable gate arrays; hardware description languages; reconfigurable architectures; ASIC like performance; FPGA; VLSI; Verilog; adder structures; modular design; multiplier structures; scalable design; statically reconfigurable processor architecture; Embedded systems; Field programmable gate arrays; Pipeline processing; Registers; Table lookup; Tuning; Architecture; CPU; Reconfigurable; VLSI; Verilog;
Conference_Titel :
Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-6084-2
DOI :
10.1109/ICECCT.2015.7226112
