Title :
Reliability improvement of Cu/low-k dual damascene interconnects using the depo/etch barrier process by newly developed I-PVD
Author :
Motoyama, K. ; Faguet, J. ; Katsuki, J. ; Chung, G. ; Tonegawa, T. ; Miyamoto, H.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Sagamihara, Japan
Abstract :
We have developed a barrier deposition process, called the depo/etch barrier process. The depo/etch barrier process is a barrier deposition process followed by an Ar etching process to remove the barrier film at the via bottom. A newly developed I-PVD tool was designed for realizing the depo/etch process by performing both deposition and etching in the same chamber. We applied the depo/etch barrier using the I-PVD tool to Cu/low-k dual damascene interconnects, and achieved a lowering of via resistance and higher endurance against EM and yield-drop with thermal cycles by the removal of the via bottom barrier.
Keywords :
copper; electromigration; integrated circuit interconnections; integrated circuit reliability; sputter deposition; sputter etching; Ar etching process; Cu; Cu/low-k dual damascene interconnects; I-PVD tool; barrier deposition process; depo/etch barrier process; electromigration endurance; reliability improvement; thermal cycles; via bottom barrier film removal; via resistance lowering; yield-drop endurance; Atomic layer deposition; Coils; Current density; Electrons; Etching; Plasma density; Radio frequency; Testing; Thermal expansion; Thermal stresses;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014953