DocumentCode :
1901502
Title :
Deep Submicron Power/Ground Networks Design for a Multi-Macro Chip
Author :
Du, Longjun ; Zhang, Xiaolin ; Su, Linlin ; Zhang, Shuai
Author_Institution :
Sch. of Electron. Inf. Eng., Beihang Univ., Beijing, China
fYear :
2010
fDate :
25-26 Dec. 2010
Firstpage :
1
Lastpage :
4
Abstract :
With the rapid increases of signal frequency and reduction of feature sizes of high-speed electronic circuits in modern VLSI design, it is becoming more and more important to design and optimize power/ground networks fast and efficiently. A method for the design of the power/ground networks at the floor-planning stage is presented, which calculates the number of pads and straps and width of straps first, and then optimizes the power/ground networks considering the Macro´s power consumption. Experimental results based on the digital television transmitter modulator design show that final IR drop is within the required range and the method is efficient and reliable.
Keywords :
CMOS integrated circuits; VLSI; high-speed integrated circuits; integrated circuit design; CMOS process technology; IR drop; VLSI design; deep submicron power-ground network design; digital television transmitter modulator design; floor-planning stage; high-speed electronic circuits; macropower consumption; multimacro chip; signal frequency; Equations; Mathematical model; Metals; Optimization; Power demand; Rails; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Engineering and Computer Science (ICIECS), 2010 2nd International Conference on
Conference_Location :
Wuhan
ISSN :
2156-7379
Print_ISBN :
978-1-4244-7939-9
Electronic_ISBN :
2156-7379
Type :
conf
DOI :
10.1109/ICIECS.2010.5678367
Filename :
5678367
Link To Document :
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