Title :
A transition-encoded dynamic bus technique for high-performance interconnects
Author :
Anders, M. ; Rai, N. ; Krishnamurthy, R. ; Borkar, S.
Author_Institution :
Intel Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
A transition-encoded dynamic bus technique enables interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short buses, while obtaining energy savings at aggressive delay targets. In a 180 nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement with this technique.
Keywords :
CMOS digital integrated circuits; VLSI; delays; integrated circuit design; integrated circuit interconnections; 180 nm; 32 bit; delay reduction; drop-in replacement; global buses; high-performance interconnects; interconnect delay reduction; microprocessor; peak-current reduction; switching energy behavior; transition-encoded dynamic bus technique; Capacitance; Decoding; Delay; Driver circuits; Flip-flops; Integrated circuit interconnections; Latches; Microprocessors; Repeaters; Variable structure systems;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015031
