Reliability oriented process and device simulations of power VDMOS transistors in Bipolar/CMOS/DMOS technology

The reliability prediction of device is really important for power device for which the functioning conditions can be severe. First, this paper presents two-dimensional process and device simulation results of power VDMOS one-cell in a Bipolar/CMOS/DMOS technology. The VDMOS process simulation is divided in three bricks: buried layer, active zone and sinker, and for more accuracy it takes into account all thermal budget. For process simulation, good results on sheet resistance, lateral and vertical doping diffusions are compared to experimental results. Electrical simulations are performed using mobility models for conduction regime, and impact ionisation model for breakdown voltage; they are in good agreement with experimental ones, confirming the good choice of models and possibility of device optimisation with TCAD approach. VDMOS transistors for automotive applications are submitted to high temperatures which can degrade electrical parameters; electrical simulations of threshold voltage, on-resistance, and saturation current are performed using previous models in function of temperature in the range 323 K to 423 K. Moreover, in this work, using process and electrical simulations of vertical power MOS (VDMOS) adapted to the process developed by STMicroelectronics, we deduced by comparison with HTRB (High Temperature Reverse Bias) analysis, the contamination of gate oxide. This approach allows evaluating the contamination level especially, degradation coming from mobile ions.