Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

Author

Suzuki, T. ; Nakahara, S. ; Iwahashi, S. ; Higeta, K. ; Kanetani, K. ; Nambu, H. ; Yoshida, M. ; Yamaguchi, K.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2002

fDate

13-15 June 2002

Firstpage

44

Lastpage

45

Abstract

Describes novel schemes developed to meet the demand for a reusable embedded SRAM core for application to a variety of SOC designs. PAS optimizes sense-amplifier activation timing by using the combination of a program and automatic control. MRAD minimizes timing-overhead by reducing the fluctuation of path-to-path delay. These schemes experimentally demonstrated a wide-operation range of 0.5 to 1.4 V and an access time of 600 ps.

Keywords

SRAM chips; application specific integrated circuits; decoding; delays; high-speed integrated circuits; integrated circuit design; memory architecture; reconfigurable architectures; timing; 0.5 to 1.4 V; 600 ps; MRAD; PAS; SOC design; access time; automatically-adjustable sense-amplifier activation scheme; high-speed reusable SRAM core; multi-reset address-driven decoding scheme; path-to-path delay; sense-amplifier activation timing; timing-overhead; wide-operation range; CMOS logic circuits; Decoding; Delay effects; Fluctuations; Manufacturing processes; Random access memory; Signal design; Timing; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015039

Filename

1015039