FinFET SRAM for high-performance low-power applications

Author

Joshi, Rajiv V. ; Williams, Richard Q. ; Nowak, Ed ; Kim, Keunwoo ; Beintner, Jochen ; Ludwig, T. ; Aller, I. ; Chuang, C.

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

69

Lastpage

72

Abstract

The SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is analyzed in detail, as compared to PD-SOI.

Keywords

MOS memory circuits; MOSFET; SRAM chips; circuit stability; low-power electronics; semiconductor device models; 90 nm; FinFET; PD-SOI; SRAM stability; double-gate FinFET; full cell cross section simulation; low active power; low standby power; low-power SRAM; planar partially-depleted SOI; Assembly; Capacitance; Circuit simulation; Councils; FinFETs; Impact ionization; Quantization; Random access memory; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356490

Filename

1356490