90% write power saving SRAM using sense-amplifying memory cell

A low power write scheme is proposed for an SRAM using seven-transistor sense-amplifying memory cells, which can save 90% of the power in write cycles when 4M SRAM is assumed. By reducing the bit line swing to 1/6 V/sub DD/ and amplifying the voltage swing by a sense-amplifier structure in a memory cell, charging and discharging component of the power of the bit lines is reduced. A 64 Kbit test chip has been fabricated and operation has been verified.