DocumentCode :
1901938
Title :
Wafer level electromigration testing on via/line structure with a poly-heated method in comparison to standard package level tests
Author :
Yap, Hin-Kiong ; Yap, Kin-Leong ; Tan, Yew-Chee ; Lo, Keng-Foo
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore, Singapore
fYear :
2003
fDate :
7-11 July 2003
Firstpage :
75
Lastpage :
79
Abstract :
In this study, we present data from alternative wafer level EM technique, poly-heated electromigration test on via chain structure. We show that there is a good correlation between conventional package level and poly-heated via test. We also present real case studies to illustrate poly-heated via test is an effective tool for process evaluation and monitoring.
Keywords :
current density; electromigration; integrated circuit packaging; integrated circuit testing; process monitoring; reliability; chain structure; current density; package level tests; polyheated method; process monitoring; reliability; wafer level electromigration testing; Current measurement; Electromigration; Force measurement; Packaging; Power measurement; Resistors; Stress measurement; Temperature control; Testing; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2003. IPFA 2003. Proceedings of the 10th International Symposium on the
Print_ISBN :
0-7803-7722-2
Type :
conf
DOI :
10.1109/IPFA.2003.1222742
Filename :
1222742
Link To Document :
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