Title :
A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme
Author :
Hsu, S.K. ; Alvandpour, A. ; Mathew, S. ; Shih-Lien Lu ; Krishnamurthy, R.K. ; Borkar, S.
Author_Institution :
Intel Labs, Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.
Keywords :
CMOS memory circuits; cache storage; 1.2 V; 130 nm; 32 KB; 4.5 GHz; CMOS circuit; DC robustness; access transistor underdrive; active leakage; dual threshold voltage scheme; dual-ported LO cache; local bitline; read delay; self reverse bias scheme; Capacitance; Decoding; Delay; Driver circuits; Inverters; Performance evaluation; Robustness; Timing; Voltage; Wires;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015041
