A comparative analysis of 6T, 7T, 8T and 9T SRAM cells in 90nm technology

Author

Premalatha, C. ; Sarika, K. ; Kannan, P. Mahesh

Author_Institution

Dept. of ECE, Anna Univ., Madhuranthagam, India

fYear

2015

fDate

5-7 March 2015

Firstpage

1

Lastpage

5

Abstract

Static Random Access Memory (SRAM) is a memory that is designed to provide high speed and low power applications. As the technology is shrinking down, the power supply is also scaled down which decreases the noise margin of the SRAM cells. The reduced noise margin further makes more leakage power in the SRAM cells. The main objective of this project is to deal with the power dissipation which occurs normally in the conventional Static Random Access Memory (SRAM) cells during the read and write operation. This problem can be solved by applying dual-threshold-voltage for 6T, 7T, 8T and 9T SRAM Cells. Their respective power dissipation and delay of these cells are calculated and compared. This is implemented in 90nm Generic Process Design Kit (GPDK) using Cadence Virtuoso Schematic Composer and the Spectre as the simulator.

Keywords

SRAM chips; transistors; 6-transistor SRAM Cells; 7-transistor SRAM Cells; 8-transistor SRAM Cells; 9-transistor SRAM Cells; Cadence Virtuoso Schematic Composer; GPDK; Generic Process Design Kit; Spectre; delays; dual-threshold-voltage; high-speed low-power applications; power dissipation; power leakage; read operation; reduced noise margin; size 90 nm; static random access memory; transistors; write operation; Delays; Random access memory; SRAM; T(transistor); access time; delay; dual-threshold-voltage; noise margin; power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-6084-2

Type

conf

DOI

10.1109/ICECCT.2015.7226147

Filename

7226147