1.5 Gbps, 5150 ppm spread spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA

Author

Sugawara, Mariko ; Ishibashi, Takayuki ; Ogasawara, Kuniaki ; Aoyama, Masahito ; Zwerg, Michael ; Glowinski, S. ; Kameyama, Y. ; Yanagita, T. ; Fukaishi, M. ; Shimoyama, S. ; Ishibashi, Takayuki ; Noma, T.

Author_Institution

NEC Electron. Inc, Santa Clara, CA, USA

fYear

2002

fDate

13-15 June 2002

Firstpage

60

Lastpage

63

Abstract

We have successfully developed a 5150 ppm spread spectrum serializer/deserializer (SerDes) physical layer (PHY) chip compliant with the serial AT attachment (ATA), The device was fabricated by a 0.13 /spl mu/m, 1.5 V CMOS process and includes a self-running, pulse-swallow phase locked loop (PLL) to generate the transmit (TX) carrier, a triple loop tracking the PLL to recover the receive (RX) clock, and a 0.3 mW current-crossover level detector to detect the 1.5 Gbps carrier for initial communication.

Keywords

CMOS integrated circuits; frequency synthesizers; peripheral interfaces; phase locked loops; signal detection; spread spectrum communication; synchronisation; telecommunication equipment; 0.13 micron; 0.3 mW; 1.5 Gbit/s; 1.5 V; CMOS process; PLL; clock recovery; current-crossover level detector; phase locked loop; physical layer; receive clock; serial AT attachment; serial ATA; spread spectrum deserializer; spread spectrum serializer; transmit carrier generation; triple loop tracking; Clocks; Detectors; Frequency conversion; Frequency locked loops; National electric code; Phase locked loops; Physical layer; Pulse generation; Spread spectrum communication; Tracking loops;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015045

Filename

1015045