Title :
A 64-kbit Dynamic MOS RAM
Author :
Arai, Eiji ; Ieda, N.
Author_Institution :
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180, Japan.
Abstract :
A 64-kbit, low power MOS RAM with single-poly cell has been developed by refined photolithographic technology, where minimum pattern dimension is 2 ¿m. The small cell area, 210 ¿m2, is realized by a novel sense circuit.
Keywords :
Conductivity; Driver circuits; Heat treatment; Laboratories; MOSFETs; Oxidation; Read-write memory; Resists; Telegraphy; Threshold voltage;
Conference_Titel :
Solid State Circuits Conference, 1977. ESSCIRC '77. 3rd European
Conference_Location :
Ulm, F.R. Germany
