• DocumentCode
    1902078
  • Title

    A 64-kbit Dynamic MOS RAM

  • Author

    Arai, Eiji ; Ieda, N.

  • Author_Institution
    Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180, Japan.
  • fYear
    1977
  • fDate
    20-22 Sept. 1977
  • Firstpage
    74
  • Lastpage
    75
  • Abstract
    A 64-kbit, low power MOS RAM with single-poly cell has been developed by refined photolithographic technology, where minimum pattern dimension is 2 ¿m. The small cell area, 210 ¿m2, is realized by a novel sense circuit.
  • Keywords
    Conductivity; Driver circuits; Heat treatment; Laboratories; MOSFETs; Oxidation; Read-write memory; Resists; Telegraphy; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference, 1977. ESSCIRC '77. 3rd European
  • Conference_Location
    Ulm, F.R. Germany
  • Print_ISBN
    380071132X
  • Type

    conf

  • Filename
    5435058
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1902078