Implementation of 64-bit Kogge Stone Carry Select Adder with ZFC for efficient area

Author

Tapasvi, B. ; Sinduri, K. Bala ; Lakshmi, B.G.S.S.B. ; Kumar, N. Udaya

Author_Institution

Dept. of ECE, SRKR Eng. Coll., Bhimavaram, India

fYear

2015

fDate

5-7 March 2015

Firstpage

1

Lastpage

6

Abstract

Carry Select Adder (CSLA) is one of the faster adder used in many data-processing processors to perform fast arithmetic functions. The speed of operation of such an adder is limited by carry propagation from input to output. This paper discusses about the implementation of linear Carry Select Adder with Kogge Stone Adder with out ZFC. The Kogge Stone parallel approach will give option to generate fast carry for intermediate stages. From the structure of linear CSLA it is clear that there is scope for reducing the area in CSLA by using a first zero finding logic. 64-bit linear CSLA architecture is implemented with out using multiplexer which reduces area with slight increase in delay. Simulation and Synthesis are carried on Modelsim 6.3 and Xilinx ISE 12.2.

Keywords

adders; carry logic; Kogge Stone carry select adder; Kogge Stone parallel approach; Modelsim 6.3; Xilinx ISE 12.2; ZFC; arithmetic functions; carry propagation; data-processing processors; linear CSLA architecture; linear carry select adder; storage capacity 64 bit; zero finding logic; Computer architecture; A first Zero finding logic(ZFC); Carry Select Adder(CSLA); Kogge Stone Adder (KSA); Regular Carry Select Adder(RCSLA); Ripple Carry Adder (RCA);

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-6084-2

Type

conf

DOI

10.1109/ICECCT.2015.7226154

Filename

7226154