Title :
Static pulsed bus for on-chip interconnects
Author :
Khellah, M. ; Tschanz, J. ; Ye, Y. ; Narendra, S. ; De, V.
Author_Institution :
Intel Labs, Microprocessor Res., Hillsboro, OR, USA
Abstract :
Static Pulsed Bus (SPB) improves delay by 15%-25% or reduces energy by 12%-25% and peak current by 26%-34%, compared to the conventional static bus (SB) scheme, for 1500 μm to 4500 μm bus lengths in a 100 nm technology. Energy savings are maintained across all data activity factors.
Keywords :
CMOS digital integrated circuits; VLSI; delays; integrated circuit interconnections; microprocessor chips; system buses; 100 nm; 1500 to 4500 micron; RC delay; VLSI; coupling capacitance multiplier factor; driver technique; energy savings; line coupling capacitance; on-chip interconnects; peak current; receiver technique; repeater technique; static pulsed bus; Added delay; Artificial intelligence; Capacitance; Clocks; Delay effects; Energy consumption; Microprocessors; Mutual coupling; Repeaters; Routing;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015051
