Triple junctions for reduced impact of offset spacer variation on CMOS device parameters

Author

Jurczak, M. ; Rooyackers, R. ; De Keersgieter, A. ; Kunnen, E. ; Henson, K. ; Richard, O. ; Dachs, C.

Author_Institution

IMEC vzw, Leuven, Belgium

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

145

Lastpage

148

Abstract

In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and after second spacers (HDD). We demonstrate that the triple junction has great potential in reducing significantly the variation of the device parameters such as drive current, off-state current, and overlap capacitance, originating from the non-uniformity of the offset spacer commonly used in CMOS devices below the 90 nm node.

Keywords

MOSFET; ion implantation; 90 nm; aggressively scaled CMOS transistors; device parameter within-wafer uniformity; drive current; ion implantation; off-state current; offset spacer nonuniformity; offset spacer variation effect reduction; overlap capacitance; second spacers; shallow trench isolation; triple junctions transistors; CMOS process; Capacitance; Costs; Degradation; Ion implantation; Thickness control; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356510

Filename

1356510