A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell

Author

Wuensche, S. ; Jacunski, M. ; Streif, H. ; Sturm, A. ; Morrish, J. ; Roberge, M. ; Clark, M. ; Nostrand, T. ; Stahl, E. ; Lewis, S. ; Heath, J. ; Wood, M. ; Vogelsang, T. ; Thoma, E. ; Gabric, J. ; Kleiner, M. ; Killian, M. ; Poechmueller, P. ; Mueller, W

Author_Institution

Infineon Technol., Essex Junction, VT, USA

fYear

2002

fDate

13-15 June 2002

Firstpage

114

Lastpage

115

Abstract

This paper describes a 512 Mb DDR SDRAM in 110 nm technology based on a highly cost efficient 8F/sup 2/ trench capacitor cell with a double gate vertical pass transistor. The product also features a bitline voltage generator using a distributed output transistor with a power supply IR-drop correction scheme. A read/write selective column activation circuit is employed to optimize high frequency operation.

Keywords

CMOS memory circuits; DRAM chips; VLSI; high-speed integrated circuits; 110 nm; 512 Mbit; 8F/sup 2/ trench capacitor cell; DDR DRAM; bitline voltage generator; cost efficient trench capacitor cell; distributed output transistor; double gate vertical pass transistor; dynamic RAM; high frequency operation; power supply IR-drop correction scheme; read/write selective column activation circuit; vertical transistor trench cell; Capacitors; Circuits; Costs; DRAM chips; Distributed power generation; Frequency; Power generation; Power supplies; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015059

Filename

1015059