Implementing array multipliers in Xilinx FPGAs

This paper discusses aspects to consider when mapping array multiplier designs to field programmable gate arrays (FPGAs). FPGAs provide configurable logic through an array of configurable logic modules interconnected by programmable routing resources and surrounded by programmable Input/Output blocks. However due to the lack of consistent structure most typical designs do not map well to FPGAs. The structure of array multipliers make them a natural fit for FPGA realization, potentially delivering the performance and utilization originally promised at the introduction of FPGAs. Two design examples are developed and mapped to the Xilinx family of FPGAs. The results of this effort are reported and projections are made as to how the designs performance vary when they are scaled for larger applications and the speed grades of the components are changed