Design and Implementation of 2×4 Network on Chip Interconnection Architecture

Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding, routing algorithm and node degree routing direction are designed. Thirdly, the programming and simulation of 2×4 NoC interconnection architecture are implemented, and it achieves pipeline operation. The result shows the correctness of the interconnection architecture design. Finally, it is chosen XC4VSX55-12ff1148 of Virtex4 to synthesize, the maximum frequency can up to 268 MHz, which provides foundation of subsequent research and application.