Design and analysis of fast carry-propagate adder under non-equal input signal arrival profile

This paper examines the design of a fast carry-propagate adder under the condition of non-equal input signals arrival. This is a common case encountered in the fast parallel multipliers where a carry-propagate adder is deployed to produce the final product. It is shown that the rules used in the past are not valid and do not result in the fastest adder. We present the analysis of those conditions and provide the rules for the fast carry-propagate adder design