Low temperature process flow optimisation for 65nm CMOS mixed-signal applications

Author

Duriez, B. ; Morin, P. ; Tavel, B. ; Froment, B. ; Gouraud, P. ; Roy, D. ; Rochereau, K. ; Difrenza, R. ; Margin, A. ; Denais, M. ; Bidaud, M. ; Stolk, P. ; Woo, M. ; Arnaud, F.

Author_Institution

Philips Semicond., Crolles, France

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

197

Lastpage

200

Abstract

In this work, a complete low temperature 65 nm process flow using a low-cost, conventional CMOS approach has been investigated. A significant global thermal budget reduction has been achieved (below 500°C), especially for the spacer, silicide-protection and salicide modules. The introduction of new materials induced a great transistor performance enhancement in both the digital and analog/mixed-signal domains. The I_off-I_on figure of merit has been improved by 20%, whereas the matching factors were reduced for both NMOS and PMOS transistors. This new optimized process flow satisfies the strict criteria of transistor reliability.

Keywords

CMOS integrated circuits; MOSFET; mixed analogue-digital integrated circuits; semiconductor device reliability; 500 degC; 65 nm; CMOS mixed-signal devices; NMOS transistors; PMOS transistors; analog transistors; digital transistors; global thermal budget reduction; low temperature process flow optimisation; matching factors; salicide modules; silicide-protection modules; spacer; transistor performance enhancement; transistor reliability; Annealing; CMOS process; Cobalt; Implants; MOS devices; MOSFETs; Nickel; Protection; Silicides; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356523

Filename

1356523