A wideband partial discharge meter using FPGA

This paper describes a hardware design of a fully digital wideband PD meter based on application of FPGA as well as design of coupling device required for PD measurements. The designed coupling device has frequency bandwidth of 1 kHz-10 MHz. The PD signal is digitalized by a fast 14-bit AID convertor sampling at frequency of 50 MSa/s. The digital samples of PD signal are read by the FPGA, subsequently filtered by a number of digital FIR filter banks and stored in a 32 MB DDR memory. On request from PC software, the FPGA send samples in reduced form through Ethernet interface for the next signal processing and evaluation all important parameters of PD analysis. The paper also describes a design of smart charge calibrator especially developed for the PD meter testing and calibration.