A robust array architecture for a capacitorless MISS tunnel-diode memory

With the aim of applying a MISS tunnel-diode cell to a high-density RAM, we studied its problems and developed three circuit techniques to solve them. The first, a hierarchical bit-line structure increases the number of memory cells in a bit-line and reduces the number of sense amplifiers. The second, a twin-dummy-cell technique generates a proper reference signal to discriminate read currents. The third, a standby-voltage control scheme reduces background currents and suppresses the degeneration of the signal current. These techniques enable a high-density RAM to use the capacitorless MISS-diode memory cell, whose effective cell area is 6F/sup 2/ (F: minimum feature size). The third technique increases the signal current from 0.25 to 0.85 compared to the original one.