Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA

This paper analyses the tradeoffs involved in the design and implementation of a High-Rate MIMO Receiver in an FPGA for BPSK, QPSK and 16-QAM modulations based on the Alamouti scheme. We designed a configurable MIMO transceiver and an AWGN generator in VHDL and determined the bit error rates of the system running in FPGA for different modulations and antenna configurations. The proposed architectures achieve around 3 Gbps for acceptable bit error rates using only 6% of a midum sized Virtex-6 FPGA. The results indicate that the Alamouti scheme is a method option for hardware implementation of a high-rate MIMO receiver and that the MIMO architectures can be optimized for each required bit error rate.