DocumentCode
1902665
Title
SESO memory: a CMOS compatible high density embedded memory technology for mobile applications
Author
Atwood, B. ; Ishii, T. ; Osabe, T. ; Mine, T. ; Murai, F. ; Yano, K.
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fYear
2002
fDate
13-15 June 2002
Firstpage
154
Lastpage
155
Abstract
SESO memory is proposed as a high density, low power embedded memory. Based on an ultra-low leakage thin-film transistor fabricated with standard CMOS logic techniques, this embedded memory has a density almost three times larger than SRAM and requires no additional processing materials. Fabricated SESO transistor characteristics are presented and a 3-transistor cell structure is analyzed, showing SESO memory to be a strong candidate as an inexpensive embedded memory.
Keywords
CMOS memory circuits; low-power electronics; mobile computing; thin film transistors; CMOS compatible embedded memory technology; CMOS logic techniques; SESO memory; SESO transistor characteristics; high density embedded memory; low power embedded memory; mobile applications; thin-film transistor; three-transistor cell structure; ultra-low leakage TFT; CMOS logic circuits; CMOS process; CMOS technology; Capacitance; Costs; Laboratories; Random access memory; Switches; Thin film transistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015071
Filename
1015071
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