CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance

This paper reports electrical results on CMOS-compatible vertical transistors and logic gates with reduced overlap capacitance. It is shown that surround-gate MOSFETs, produced using the fillet local oxidation process (FILOX), have lower gate/drain overlap capacitance and consume less silicon area than comparable lateral MOSFETs. Novel logic gate structures, based on partially removing the polysilicon surround gate, are described and characterised.