Title :
/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs
Author :
Kanno, Y. ; Mizuno, H. ; Oodaira, N. ; Yasu, Y. ; Yanagisawa, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
To provide low-cost system solutions together with a 0.13-/spl mu/m dual-t/sub ox/ CMOS and multi-chip package (MCP) technologies, a new, so-called /spl mu/I/O architecture was developed. The /spl mu/I/O provides a common interface throughout the module and, thus, enables high design reusability and hierarchical I/O design for MCPs. The /spl mu/I/O includes a signal-level converter for integrating wide-voltage-range (0.75-1.3 or 1.5-3.6 V) circuit blocks, and a signal wall function for turning off each block independently - without invalid signal transmission - by using an internal power switch.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit packaging; leakage currents; mixed analogue-digital integrated circuits; /spl mu/I/O architecture; 0.13 micron; 0.75 to 1.3 V; 1.5 to 3.6 V; CMOS multi-chip package; design reusability; hierarchical I/O design; internal power switch; invalid signal transmission; signal wall function; signal-level converter; wide-voltage-range system-on-a-package; CMOS technology; Circuits; Packaging; Switching converters; Turning;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015075
