• DocumentCode
    1902764
  • Title

    On the platform specificity of STM instrumentation mechanisms

  • Author

    Wenjia Ruan ; Yujie Liu ; Chao Wang ; Spear, M.

  • Author_Institution
    Lehigh Univ., Bethlehem, PA, USA
  • fYear
    2013
  • fDate
    23-27 Feb. 2013
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    Supporting atomic blocks (e.g., Transactional Memory (TM)) can have far-reaching effects on language design and implementation. While much is known about the language-level semantics of TM and the performance of algorithms for implementing TM, little is known about how platform characteristics affect the manner in which a compiler should instrument code to achieve efficient transactional behavior. We explore the interaction between compiler instrumentation and the performance of transactions. Through evaluation on ARM/Android, SPARC/Solaris, IA32/Linux and IA32/MacOS, we show that the compiler must consider the platform when determining which analyses, transformations, and optimizations to perform. Implementation issues include how TM library code is reached, how per-thread TM metadata is stored and accessed, and how a library switches between modes of operation. We also show that different platforms favor different TM algorithms, through the introduction of a new TM algorithm for the ARM processor. Our findings will affect compiler and TM library designers: to achieve peak performance for transactions, the compiler must perform platform-dependent analysis, transformation, and optimization, and the interface to the TM library must differ according to platform.
  • Keywords
    concurrency control; meta data; multi-threading; operating systems (computers); parallel algorithms; parallel languages; program compilers; programming language semantics; ARM processor; ARM/Android; IA32/Linux; IA32/MacOS; SPARC/Solaris; STM instrumentation mechanisms; TM algorithm; TM library code; algorithm performance; compiler instrumentation; language design; language implementation; language-level semantics; per-thread TM metadata; platform-dependent analysis; platform-dependent optimization; platform-dependent transformation; transaction performance; transactional behavior; transactional memory; Algorithm design and analysis; Instruction sets; Instruments; Libraries; Linux; Optimization; Throughput; Transactional Memory, ARM, relaxed memory consistency, thread; local storage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Code Generation and Optimization (CGO), 2013 IEEE/ACM International Symposium on
  • Conference_Location
    Shenzhen
  • Print_ISBN
    978-1-4673-5524-7
  • Type

    conf

  • DOI
    10.1109/CGO.2013.6495000
  • Filename
    6495000