On-chip efficient Round-Robin scheduler for high-speed interconnection

Due to the simplicity of scheduling, the buffered crossbar is becoming attractive for high-speed communication system. Although the previously proposed Round-Robin algorithms achieve 100% throughput under uniform traffic, they can not achieve a satisfactory performance under non-uniform traffic. In this paper, we propose an efficient Round-Robin scheduling algorithm based on binary-tree scheme where service policy is applied to improve Quality-of-Service. With the proposed scheduling algorithm, the searching time-complexity of O(1) (one clock cycle) and 100% throughput under non-uniform traffic can be obtained. Based on a binary-tree structure, the design achieves high-speed data rate at Tbps, and simpler design with combinational circuits. The design has been simulated on both FPGA-based (Virtex 5) and Silicon-based technology (0.18 μm). The synthesis results show that consumed resources varied from 11 to 533 slices and from 46 to 1686 2-NAND gates for crossbars of size 4× 4 to 128 × 128. Critical path delays from 0.72 to 4.52 ns for FPGA-based and from 1.33 to 4.0 ns for silicon-based have obtained for the design.