Title :
NBTI reliability analysis for a 90 nm CMOS technology
Author :
Puchner, H. ; Hinh, L.
Author_Institution :
Technol. R&D, Cypress Semicond., San Jose, CA, USA
Abstract :
We present a comprehensive empirical study to investigate the impact of negative bias temperature instability (NBTI) on device performance and reliability. The NBTI lifetime is calculated for different lifetime criteria such as 10% Idsat or 50 mV Vt shift for different bias conditions, temperature, duty cycles, gate length, and gate width dependence, to allow a true comparison between different methodologies. Finally, a circuit level implementation approach is presented to estimate the NBTI device level reliability at a circuit level. Therefore, the absolute threshold voltage shift is calculated and inserted into the spice level transistor model for corner simulations.
Keywords :
MOSFET; semiconductor device models; semiconductor device reliability; thermal stability; 90 nm; CMOS technology; NBTI lifetime; NBTI reliability analysis; PMOSFET transistors; bias conditions; device circuit level reliability; duty cycles; gate length; gate width; negative bias temperature instability; spice level transistor model; temperature; threshold voltage shift; Analytical models; CMOS technology; Degradation; Extrapolation; MOSFET circuits; Niobium compounds; Stress; Temperature; Threshold voltage; Titanium compounds;
Conference_Titel :
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN :
0-7803-8478-4
DOI :
10.1109/ESSDER.2004.1356538
