Title :
An improved gate capacitance model for GaAs MESFETs
Author_Institution :
Vitesse Semicond. Corp., Camarillo, CA, USA
Abstract :
This paper describes the measurement and modeling of gate capacitance for self-aligned, LDD GaAs EFETs and DFETs. An improved, scalable gate capacitance model is presented which is suitable for compact device simulation.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; capacitance; gallium arsenide; semiconductor device models; DFETs; EFETs; GaAs; GaAs MESFETs; compact device simulation; depletion devices; enhancement devices; gate capacitance model; measurement; scalable model; self-aligned LDD FET; Capacitance measurement; Equations; FETs; Gallium arsenide; Integrated circuit modeling; Logic devices; MESFETs; Scattering parameters; Temperature distribution; Threshold voltage;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1996. Technical Digest 1996., 18th Annual
Conference_Location :
Orlando, FL, USA
Print_ISBN :
0-7803-3504-X
DOI :
10.1109/GAAS.1996.567843
