Title :
Selective node engineering for chip-level soft error rate improvement [in CMOS]
Author :
Karnik, T. ; Vangal, S. ; Veeramachaneni, V. ; Hazucha, P. ; Erraguntla, V. ; Borkar, S.
Author_Institution :
Circuit Res., Intel Labs., Hillsboro, OR, USA
Abstract :
This paper presents a technique to selectively engineer sequential or domino nodes in high performance circuits to improve soft error rate (SER) induced by cosmic rays or alpha particles. In 0.18 /spl mu/m process, the SER improvement is as much as 3/spl times/ at the cell-level, 1.8/spl times/ at the block-level and 1.3/spl times/ at the chip-level without any penalty in performance or area, and <3% power penalty. The node selection, hardening and SER quantification steps are fully automated.
Keywords :
CMOS logic circuits; alpha-particle effects; cellular arrays; cosmic ray interactions; radiation hardening (electronics); sequential circuits; 0.18 micron; CMOS; SER improvement; alpha particles; block-level; cell-level; chip-level; chip-level soft error rate improvement; cosmic rays; domino nodes; hardening; power penalty; selective node engineering; sequential nodes; Alpha particles; Capacitance; Capacitors; Circuits; Cosmic rays; Error analysis; Feedback; Latches; Logic; Voltage;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015084
