Threshold-voltage balance for minimum supply operation

Author

Ono, G. ; Miyazaki, M.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

2002

fDate

13-15 June 2002

Firstpage

206

Lastpage

209

Abstract

The difference between the threshold voltages (Vt) of PMOS and NMOS transistor is a critical issue in the operation of low voltage circuits. The P/N Vt balancing profit is analyzed in terms of sub-threshold leakage current, minimum supply voltage, and static noise margin. Balancing the P/N Vt reduces the lowest required supply voltage by 0.15-0.3 V. The use of our proposed Vt matching scheme enables CMOS LSI minimum supply voltage processing at 0.1 V.

Keywords

CMOS integrated circuits; VLSI; integrated circuit noise; large scale integration; leakage currents; low-power electronics; 0.1 V; CMOS LSI; LV circuits; NMOS transistors; PMOS transistors; VLSI; Vt matching scheme; low voltage circuits; minimum supply operation; static noise margin; subthreshold leakage current; system LSIs; threshold-voltage balance; CMOS technology; Circuit noise; Circuit simulation; Delay; Fluctuations; Large scale integration; Leakage current; Low voltage; MOSFETs; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015085

Filename

1015085

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1903055