Title :
Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology
Author :
Sasaki, Y. ; Satoh, M. ; Kuramoto, M. ; Kikuchi, F. ; Kawashima, T. ; Masuda, H. ; Yano, K.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
The impact of crosstalk on the delay was examined by measuring a test chip manufactured with a 0.13-/spl mu/m-node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: (1) consideration of degradation change dependent on relative-signal-arrival-time over a wide range, (2) static timing analysis (STA) based operation, and (3) quantitative estimation of the degradation accumulation caused by multiple aggressors. A candidate for such simulation technology is provided. and its highly precise characteristic is demonstrated through measurements and simulations. In a test structure with a two-aggressor crosstalk, the maximum error between the measured and simulated degradations was reduced to less than one sixth of that with a conventional method.
Keywords :
VLSI; circuit simulation; crosstalk; delays; logic simulation; timing; 0.13 micron; crosstalk delay analysis; degradation accumulation; multiple aggressors; precise gate-level simulation technology; quantitative estimation; relative-signal-arrival-time; static timing analysis; two-aggressor crosstalk; Analytical models; Circuit simulation; Crosstalk; Degradation; Delay effects; Delay estimation; Semiconductor device measurement; Signal processing; Testing; Timing;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015086
