Back-gated SOI technology: power-adaptive logic and non-volatile memory using identical processing

Author

Avci, Uygar ; Kumar, Arvind ; Liu, Haitao ; Tiwari, Sandip

Author_Institution

Sch. of Appl. & Eng. Phys., Cornell Univ., Ithaca, NY, USA

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

285

Lastpage

288

Abstract

A back-gated scalable silicon-on-insulator (SOI) technology that provides a non-volatile memory, logic with adaptive power-performance trade-off and buried interconnectivity is reported. The back-gate approach has the following characteristics: (1) a logic transistor whose threshold voltage modulation allows adaptive power control of digital and analog circuits, (2) a non-volatile memory where the read-transistor scaling is decoupled from storage constraints, (3) good SOI thickness control, (4) speed degradation due to alignment tolerances lower than 16%, (5) a new analog design approach to achieve adaptive low voltage operation within digital constraints.

Keywords

field effect memory circuits; integrated circuit interconnections; logic circuits; low-power electronics; random-access storage; silicon-on-insulator; CMOS technology; SOI thickness control; Si-SiO₂; adaptive power control; alignment tolerance speed degradation; analog low voltage operation; back-gated SOI technology; buried interconnectivity; logic transistor threshold voltage modulation; nonvolatile memory; operational amplifier; power-adaptive logic; silicon-on-insulator; storage constraint decoupled read-transistor; Adaptive control; Digital modulation; Integrated circuit interconnections; Logic circuits; Logic design; Nonvolatile memory; Power control; Programmable control; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356545

Filename

1356545