Title :
Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing
Author :
Tschanz, J. ; Yibin Ye ; Liqiong Wei ; Govindarajulu, V. ; Borkar, N. ; Burns, Steven ; Karnik, T. ; Borkar, S. ; De, V.
Author_Institution :
Microprocessor Res., Intel Labs., Hillsboro, OR, USA
Abstract :
Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.
Keywords :
circuit optimisation; integrated circuit design; microprocessor chips; design optimizations; dual-V/sub T/ allocation; high performance microprocessor; leakage power; optimum design; processor frequency; transistor sizing; Circuit noise; Clocks; Delay; Design automation; Design optimization; Frequency; Logic circuits; Manufacturing processes; Microprocessors; Process design;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015089
