Phase-change memory technology for embedded applications

Author

Ottogalli, F. ; Pirovano, A. ; Pellizzer, F. ; Tosi, M. ; Zuliani, P. ; Bonetalli, P. ; Bez, R.

Author_Institution

Central R&D, STMicroelectronics, Agrate Brianza, Italy

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

293

Lastpage

296

Abstract

A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 μm CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10× read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.

Keywords

MOS memory circuits; random-access storage; solid-state phase transformations; 0.18 micron; 10 ns; 20 ns; 4 Mbit; CMOS technology; MOSFET selector; RESET pulse cell endurance effects; SET operation; embedded memory; nonvolatile memories; ovonic unified memory; p-trench PCM cell; phase-change memory technology; write time; CMOS process; CMOS technology; MOSFET circuits; Nonvolatile memory; Phase change materials; Phase change memory; Read-write memory; Research and development; Split gate flash memory cells; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356547

Filename

1356547