Integration and cell characteristics for high density PRAM

Author

Ryoo, K.C. ; Hwang, Y.N. ; Lee, S.-H. ; Lee, Suyoun ; Ahn, S.J. ; Song, Y.J. ; Park, J.H. ; Jeong, C.W. ; Shin, J.M. ; Jeong, W.C. ; Koh, K.H. ; Jeong, G.T. ; Jeong, H.S. ; Kim, K.N.

Author_Institution

Semicond. R&D Center, Sarnsung Electron. Co., Ltd., Kyunggi-Do, South Korea

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

297

Lastpage

300

Abstract

A 64 Mb phase change random access memory, based on 0.18 μm technology is developed. We proposed several key factors such as BEC and GST cell size, contributing to stabilization of writing current for reversible cell transition. By reducing writing current to 1.1 mA through such optimization, we have developed a 64 Mb PRAM. With memory functions and reliability tests, the feasibility for developing high-density 64 Mb PRAM is presented.

Keywords

circuit optimisation; circuit stability; integrated circuit reliability; order-disorder transformations; random-access storage; 0.18 micron; 1.1 mA; 64 Mbit; BEC; GST cell size; Ge-Sb-Te; PRAM reliability; high density PRAM; nonvolatile RAM; optimization; phase change random access memory; reversible cell transition; writing current stabilization; Amorphous materials; Crystalline materials; Driver circuits; Electrodes; Laser beams; Optical materials; Phase change materials; Phase change random access memory; Testing; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356548

Filename

1356548