DocumentCode
1903213
Title
A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption
Author
Hong-Wei Chiu ; Shey-Shi Lu
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2002
fDate
13-15 June 2002
Firstpage
226
Lastpage
229
Abstract
The state-of-the-art noise figures of 2.17 dB and 3.0 dB at 5 GHz band from monolithic CMOS LNA´s with 10 mW dissipation on thin (/spl sim/ 20 /spl mu/m) and normal (750 /spl mu/m) substrates are presented. Excellent Input return loss (S/sub 11/) of -45 dB, high P/sub 1dB/ of -8.3 dBm and large IIP3 of 0.3 dBm were also obtained. The excellent performance of the LNA´s is attributed to the methodology we developed.
Keywords
CMOS analogue integrated circuits; MMIC amplifiers; integrated circuit design; integrated circuit noise; low-power electronics; 10 mW; 2.17 to 3 dB; 20 micron; 5 GHz; 750 micron; C-band LNAs; DC power consumption; low noise amplifiers; low power consumption; monolithic CMOS LNA; CMOS technology; Circuit noise; Computer networks; Energy consumption; FETs; Frequency; Impedance matching; Inductors; Noise figure; Noise measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015091
Filename
1015091
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