Delay fault testability modeling with temporal logic

To ensure the quality of manufactured integrated circuits, it is important that designs be delay fault testable. A formal verification technique such as temporal logic can help avoid the large cost of dynamic simulation. Temporal logic is a formalism for evaluating the temporal behavior of systems. STeP, Stanford Temporal Prover, is a system developed at Stanford University to support computer-aided formal verification of concurrent and reactive systems based on temporal logic specification. The application of temporal logic and STeP to delay fault testability modeling and analysis is presented