ISDB-T receiver architecture and VLSI implementation in 65 nm CMOS, for Fixed-Reception high definition Digital Television

In this paper we present Architecture, Algorithms and VLSI implementation in CMOS 65 nm, of an ISDB-T Digital Receiver for Fixed-Reception of Digital Television. Furthermore, we show the System Test environment used to validate the FPGA and VLSI designs. The Receiver can work on Zero-IF or IF modes and several blocks are based on CORDIC Algorithm. It is the first VLSI implementation of an ISDB-T receiver in Brazil, in full compliance with the so-called ISDB-Tb. Furthermore, it is a landmark within IC-Brazil Program, which aims the development of an ecosystem in Microelectronics, capable of insert Brazil in the International Semiconductor landscape.