The Air Spacer Technology for Improving the Cell Distribution in 1 Giga Bit NAND Flash Memory

Author

Kang, Daewoong ; Shin, Hyungcheol ; Chang, Sungnam ; An, Jungjoo ; Lee, Kyongjoo ; Kim, Jinjoo ; Jeong, Eunsang ; Kwon, Hyukje ; Lee, Eunjung ; Seo, Seunggun ; Lee, Wonseong

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ.

fYear

2006

fDate

12-16 Feb. 2006

Firstpage

36

Lastpage

37

Abstract

Recently the cell integration density of NAND flash memory increases rapidly due to its simple structure suitable for high resolution lithography. However as the cell integration density increases, NAND flash memory cell shows the problem of increased parasitic capacitance between the cells. The problems are generated by the floating-gate interference during cell operation. In order to reduce the floating gate interference, it is necessary to adopt low-k dielectric material. In this work, we would like to propose the air spacer which has the lowest dielectric constant. We applied the air spacer technology on poly-Si/W six stack gate of 90 nm design-rule NAND flash device for the first time, which improved the cell operation characteristics

Keywords

NAND circuits; dielectric materials; flash memories; low-k dielectric thin films; 1 Gbit; 90 nm; NAND flash memory; air spacer technology; cell distribution; cell integration density; floating gate interference; high resolution lithography; low-k dielectric material; parasitic capacitance; poly-Si/W six stack gate; Capacitors; Dielectric constant; Interference; Nonvolatile memory; Parasitic capacitance; Pulse measurements; Random access memory; Silicon compounds; Space technology; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st

Conference_Location

Monterey, CA

Print_ISBN

1-4244-0027-9

Type

conf

DOI

10.1109/.2006.1629483

Filename

1629483