DocumentCode
1903831
Title
A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques
Author
Tang, S. ; Hsu, S. ; Ye, Y. ; Tschanz, J. ; Somasekhar, D. ; Narendra, S. ; Shih-Lien Lu ; Krishnamurthy, R. ; De, V.
Author_Institution
Microprocessor Res., Intel Labs., Hillsboro, OR, USA
fYear
2002
fDate
13-15 June 2002
Firstpage
320
Lastpage
321
Abstract
Clock frequency of a multi-ported, 256/spl times/32b dynamic register file in a 100nm technology is improved by 50%, compared to the best dual-V/sub T/ (DVT) design, using LBSF and SFN leakage-tolerant circuit techniques for LBL and GBL. Total transistor width of the full LBSF design is the smallest.
Keywords
MOS digital integrated circuits; clocks; integrated circuit design; leakage currents; microprocessor chips; 100 nm; 32 bit; 8192 bit; GBL; LBL; LBSF; SFN; clock frequency; leakage bypass; leakage-tolerant dynamic register file; microprocessor cores; source follower NMOS; stack forcing; transistor width; Circuit noise; Delay; Noise figure; Noise measurement; Noise robustness; Registers; Tiles; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015115
Filename
1015115
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