DocumentCode
1903835
Title
Ultra-Short Pulses Improving Performance and Reliability in Flash memories
Author
Chimenton, Andrea ; Irrera, Fernanda ; Olivo, Piero
Author_Institution
Universita di Ferrara
fYear
2006
fDate
12-16 Feb. 2006
Firstpage
46
Lastpage
47
Abstract
Reliability and performance of both NAND and NOR flash memories strongly depend on the physics of Fowler Nordheim (FN) tunneling, a mechanism widely used in writing operations. In fact, the large number of involved cells and the strong sensitivity to technological parameter variations cause wide threshold voltage distributions after FN tunneling. Overerase, erratic phenomena and tunnel oxide degradation (TOD) with long-term consequences on data retention are examples of FN related issues. Recently it has been shown that the use of high voltage ultra-short pulses (<1mus) separated by a recovery time (gt;10mus) (hereafter called pulsed operation, PO) can improve reliability by reducing TOD, and, hence, SILC. Performance and reliability improvement have been demonstrated on 7 nm and 3.5 nm tunnel oxides showing the wide range of applicability of the methodology. Nevertheless, so far, these important studies have only involved single cells or small arrays of a few thousands of cells on a wafer. This work shows, for the first time, experimental results based on the application of PO on large arrays of flash cells. Issues and limits as well as improvements in terms of reliability and performance are here discussed
Keywords
NAND circuits; NOR circuits; circuit reliability; flash memories; tunnelling; 3.5 nm; 7 nm; Fowler Nordheim tunneling; NAND flash memories; NOR flash memories; data retention; erratic phenomena; flash memory performance; flash memory reliability; high voltage ultra-short pulses; pulsed operation; tunnel oxide degradation; ultrashort pulses; writing operations; Degradation; Flash memory; Performance evaluation; Physics; Semiconductor device measurement; Test equipment; Testing; Threshold voltage; Tunneling; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st
Conference_Location
Monterey, CA
Print_ISBN
1-4244-0027-9
Type
conf
DOI
10.1109/.2006.1629487
Filename
1629487
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