On the different time dependence of interface trap generation and charge thapping during hot carrier degradation in CMOS

In this paper both I-V and charge pumping (CP) measurements are used to study the time dependence of the hot carrier degradation of n-and pMOSFET´s under various stress conditions. It will be shown that for the interface trap generation, in all cases a power law relationship is obtained, while the buildup of positive and negative charge behaves logarithmically with time. The time dependence of the degradation monitored with I-V will of course be determined by the dominant degradation mechanism. in this way, the duality between the degradation of n- and pMOSFET´s is confirmed. Also the relevance of these time dependencies for dynamic degradation is treated.