Design of an IEEE 802.15.3c baseband processor in FPGA

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using Matlab/Simulink to extract important hardware characteristics for the FPGA implementation.